1. Field of the Invention
The present invention relates generally to protection of integrated circuit elements from damage due to electrostatic discharge (ESD). More particularly, the present invention relates to an ESD protection circuit suitable for use in CMOS integrated circuit input/output (I/O) buffers.
2. Description of Related Art
The problem of Electrostatic Discharge (ESD) damage is particularly severe in metal-oxide-semiconductor (MOS) integrated circuits. As a result, MOS I/O buffers generally include some form of ESD protection circuit.
One type of ESD protection circuit in accordance with the prior art is shown in FIG. 1(a), a single exemplary integrated circuit output pad 10 provides an interconnection between internal logic circuitry and the external pins of the device. The internal logic circuitry shown includes an operative PMOS field effect transistor (FET) M1 and an operative NMOS FET M2. The word "operative" as used herein will refer to internal integrated circuit transistors which are used for logic or other normal functional operations within the integrated circuit. The operative transistors should be distinguished from the "protective" transistors which are those used solely for ESD protection purposes. The exemplary circuit of FIG. 1(a) includes two NMOS protective transistors M3 and M4. Transistor M3 is a thick field oxide NMOS FET which has a gate connected to the output pad 10. The drain of M3 is connected to the gate of transistor M4, a thin oxide NMOS FET. The drain of transistor M4 is connected to output pad 10 and the sources of both transistors M3 and M4 are connected to a ground potential 18 within the integrated circuit.
Operative transistor M1 and M2 are connected in series between a supply voltage potential 16 and ground potential 18. The gates of operative transistors M1 and M2 receive internal logic signals from other parts of the integrated circuit via signal input lines 12, 14 respectively. M1 and M2 are arranged in an invertor configuration commonly used in CMOS output buffers. If signal input lines 12, 14 were tied together to a single logic line, the inverse of the value on the logic line would be continuously supplied to output pad 10.
Protective transistors M3 and M4 become operative during an ESD event. The high voltage typically generated by an ESD event turns on the thick field oxide NMOS FET M3. The current passing through transistor M3 in turn affects the voltage at the gate of transistor M4. The voltage at the gate of M4 is controlled in order to turn it on and discharge the charge present at the output pad 10 from the ESD event. Transistor M3 is constructed as a thick field oxide device in order to prevent damage to the oxide during the ESD event. Transistor M4 may be a thin oxide device constructed in a manner similar to that used to construct operative transistor M2. An N-well resistor R1 is typically tied to the gate of transistor M4 in order to eliminate any potential false triggering or leakage through M4 during normal operation of the output buffer.
The above described circuitry controls the gate voltage present in thin oxide devices during an ESD event at their drains. The ESD event induces a voltage from displacement current as a result of parasitic capacitance between the thin oxide gate polysilicon and the drain diffusion (drain overlap capacitance). The thick field oxide device is a voltage regulator which controls the potential on the thin oxide polysilicon gate. This technique for controlling the thin oxide gate potential is known to those skilled in the art as "dynamic gate coupling". In order to optimize the desired protection in a given application, it is necessary to, in effect, "custom design" the parameters of M3 and M4 to satisfy the requirements of that application. It is therefore necessary, under current practice, to expend significant additional design effort when using the protective circuitry of FIG. 1(a). A single standardized design is generally not suitable for a large number of applications. Both design and manufacturing costs are increased as a result.
A second type of prior art protection circuit is shown in FIG. 1(b). The operation of this circuit is similar to that of FIG. 1(a), except the "unused" protective FET M4 is now also an operational FET. The FET M2 serves at both an operative FET, accepting internal logic signals form other parts of the integrated circuit via signal input lines 20 and invertor 22. The output of invertor 22 is applied to the gate of M2 and the drain of thick field oxide NMOS FET M3. The protective operation of the FETS M2 and M3 are similar to that described above. An ESD pulse coupled to the gate of M3 regulates a voltage on the gate of M2. FET M3 controls the impedance of M2 during the ESD event, providing a measure of protection during an ESD event.
The NMOS transistors M2, M3 and M4 in FIGS. 1(a) and 1(b) are shown with their parasitic lateral NPN bipolar transistors in phantom. The lateral bipolars arise as a consequence of the construction of the NMOS devices. A NMOS device typically consists of two N+ regions in a P-well formed on a P-type substrate. The two N+ regions are thus separated by a P region, creating a lateral NPN bipolar transistor. The parasitic bipolar includes a base resistor R.sub.b the value of which is a function of the resistivity of the P-well material. The parasitic bipolar is triggered during the ESD pulse and provides a high current carrying capacity during avalanche mode. Although each NPN transistor includes a lateral bipolar parasitic, the operation of only a single parasitic during an ESD event will cause an excessive increase in the heating of the parasitic, which can cause its metallization to melt, shorting to the drain or source, or otherwise damaging the NMOS device. It is therefore necessary to design the NMOS FETS such that the maximum number of lateral bipolar parasitics trigger simultaneously during an ESD event. An approach disclosed in "Dynamic Gate Couple of NMOS for Efficient Output ESD Protection" by C. Duvvury and C. Diaz, Proceedings of the IRPS, 1992, pp. 141-150, found that optimal lateral bipolar triggering is achieved by controlling the voltage at the gate of M2, as determined by the size of the field oxide NMOS FET M3. These additional design efforts are therefore required under present practice in achieving optimal protection for a given application.
Another typical prior art ESD protection circuit uses a thin gate oxide NMOS FET with a grounded gate. One such circuit is disclosed in U.S. Pat. No. 5,159,518. As shown in FIGS. 1 and 3 of the '518 patent a grounded gate NMOS device is combined with a series input resistor and an input diode to provide ESD protection for a CMOS integrated circuit input buffer.
Other presently available ESD protection circuits utilize a thick field oxide NMOS FET. The thick field oxide NMOS FET generally has both its gate and its drain connected to the pad, and its source connected to ground. Another example of this type of circuit is disclosed in U.S. Pat. No. 4,819,047. See FIGS. 4 and 5, and column 6, lines 19-54.
The prior art protection circuit disclosed in U.S. Pat. No. 4,807,080 combines a grounded gate NMOS FET with a thick field oxide NMOS FET. See FIG. 5 and column 5, lines 15-65. However, even with both of these devices, the protective circuit still requires a series diffusion resistor to provide adequate input buffer ESD protection.
Each of the above prior art designs are limited in the amount of ESD protection they can provide, given the basic protection elements discussed above. As a result, most include significant additional circuitry which adds cost and complexity to the integrated circuit. The additional circuitry may also adversely impact the functional performance of the integrated circuit, as is the case with a series diffusion resistor.
In addition, none of the circuits discussed above can provide optimal protection in terms of proper triggering of the maximum number of lateral bipolar transistors without substantial redesign for different applications. There is no presently available standardized technique for providing ESD protection in CMOS input/output (I/O) buffers. It is therefore necessary to employ a variety of different protection techniques in order to meet design goals. The cost of CMOS devices is thereby adversely affected.
It can be seen from the above that a need exists for a simple and inexpensive means of providing a standardized ESD protection circuit suitable for use in a wide variety of applications. A further need exists for providing a means of enhancing the protection provided by NMOS output buffer FETS without adversely impacting circuit performance or production cost.